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| kinetis k82 sub-family high performance arm? cortex?-m4f mcu with up to 256kb of flash, 256kb of sram, full speed usb connectivity, enhanced security, and quadspi for interfacing to serial nor flash the k82 sub-family extends kinetis products with new hardware security mechanisms including decryption from serial nor flash memory, aes128, aes256 with side band attack protection, and elliptical curve cryptography acceleration. these advancements are done while maintaining a high level of compatibility with previous kinetis devices. the mcus range in total flash space upto 256kb and have 256kb of sram. the quadspi interface supports connections to non-volatile memory for data or code. the extended memory resources and new security features allow developers to enhance their embedded applications with greater capability. performance ? up to 150 mhz arm cortex-m4 based core with dsp instructions and single precision floating point unit memories and memory expansion ? up to 256 kb program flash with 256 kb ram ? flexbus external bus interface and sdram controller ? dual quadspi with otf decryption and xip ? 32 kb boot rom with built in bootloader ? supports sdr and ddr serial flash and octal configurations system and clocks ? multiple low-power modes ? memory protection unit with multi-master protection ? 3 to 32 mhz main crystal oscillator ? 32 khz low power crystal oscillator ? 48 mhz internal reference timers ? one 4 ch-periodic interrupt timer ? two 16-bit low-power timer pwm modules ? two 8-ch motor control/general purpose/pwm timers ? two 2-ch quadrature decoder/general purpose timers ? real-time clock with independent 3.3v power domain ? programmable delay block human-machine interface ? low-power hardware touch sensor interface (tsi) ? general-purpose input/output analog modules ? one 16-bit sar adcs, two 6-bit dac and one 12-bit dac ? two analog comparators (cmp) containing a 6-bit dac and programmable reference input ? voltage reference 1.2v operating characteristics ? main vdd voltage and flash write voltage range:1.71vC3.6 v ? temperature range (ambient): -40 to 105c ? independent v ddio for porte (quadspi): 1.71vC3.6 v communication interfaces ? usb full-/low-speed on-the-go controller ? secure digital host controller (sdhc) and flexio ? one i2s module, three spi, four i2c modules and five lpuart modules security ? lp trusted crypto (ltc) hardware accelerators supporting aes, des, 3des, rsa and ecc ? hardware random-number generator ? supports des, aes, sha accelerator (cau) ? multiple levels of embedded flash security mk82fn256vdc15 mk82fn256vll15 mk82fn256vlq15 MK82FN256CAX15 121 xfbga (dc) 8 x 8 x 0.5 mm pitch 0.65 mm 100 lqfp (ll) 14 x 14 x 1.7 pitch 0.5mm 144 lqfp (lq) 20 x 20 x 1.6 pitch 0.5 mm 121 wlcsp (ax) 4.64 mm x 4.53 mm nxp semiconductors k82p121m150sf5 data sheet: technical data rev. 2, 11/2016 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
ordering information part number memory maximum number of i\o's flash sram mk82fn256vdc15 256 kb 256 kb 87 mk82fn256vll15 256 kb 256 kb 66 MK82FN256CAX15r 1 256 kb 256 kb 87 mk82fn256vlq15 2 256 kb 256 kb 102 1. the 121-pin wlcsp package for this product is not yet available, however it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. 2. the 144-pin lqfp package for this product is not yet available, however it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. device revision number device mask set number sim_sdid[revid] jtag id register[prn] 1n03p 0001 0001 related resources type description resource product selector the product selector lets you find the right kinetis part for your design. k-series product selector fact sheet the fact sheet gives overview of the product key features and its uses. k8x fact sheet reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. k82p121m150sf5rm 1 data sheet the data sheet includes electrical characteristics and signal connections. this document. chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_k_1n03p 1 package drawing package dimensions are provided in package drawings. ? lqfp 100-pin: 98ass23308w 1 ? xfbga 121-pin: 98asa00595d 1 ? lqfp 144-pin: 98ass23177w 2 ? wlcsp 121-pin: under development 2 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. 2. this package for this product is not yet available, however it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. 2 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors cryptographic accelerator (cau) trace port jtag & serial wire swj-dp tpiu arm cortex m4 ppb ahb-ap etm dsp fpu nvic itm fpb dwt system icode dcode 192 kbyte 64 kbyte sram mux cache 8 kbyte m0 m1 8 kbyte m3 m2 m4 pit wic rtc osc osc irc 48 mhz mcg irc 4 mhz pll fll dma mux x2 edma esdhc usb/ fs/ls dcd crossbar switch (xbs) system memory protection unit (mpu) s1 s5 s0 otfad qspi boot rom flash controller x128 sdramc flexbus flash 256 kbyte s2 s3 bme2 rgpio ahb to ips 0 ahb to ips 1 pitpdb emvsim x2 spi x3 6-bit dac & cmp x2 flexio lp trusted cryptography 16-bit adc vref i2c x4 lpuart x5 flextimer x4 trng tsi cmt tpm x2 crc 12-bit dac i2s rtc low-power timer x2 pmc lp trusted cryptography supports: -aes128/192/256 -pkha rsa/ecc with timing equalization protection -3des s4 figure 1. k82 block diagram kinetis k82 sub-family, rev. 2, 11/2016 3 nxp semiconductors table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 5 1.4.1 recommended por sequencing .................... 6 2 general................................................................................... 8 2.1 ac electrical characteristics............................................. 8 2.2 nonswitching electrical specifications.............................. 9 2.2.1 voltage and current operating requirements..... 9 2.2.2 hvd, lvd and por operating requirements.... 10 2.2.3 voltage and current operating behaviors.......... 11 2.2.4 power mode transition operating behaviors...... 12 2.2.5 power consumption operating behaviors.......... 14 2.2.6 electromagnetic compatibility (emc) specifications..................................................... 20 2.2.7 designing with radiated emissions in mind....... 20 2.2.8 capacitance attributes...................................... 20 2.3 switching specifications................................................... 21 2.3.1 device clock specifications............................... 21 2.3.2 general switching specifications....................... 21 2.4 thermal specifications..................................................... 23 2.4.1 thermal operating requirements....................... 23 2.4.2 thermal attributes............................................. 23 3 peripheral operating requirements and behaviors.................. 24 3.1 core modules.................................................................. 24 3.1.1 debug trace timing specifications..................... 24 3.1.2 jtag electricals................................................ 25 3.2 clock modules................................................................. 28 3.2.1 mcg specifications........................................... 28 3.2.2 irc48m specifications...................................... 31 3.2.3 oscillator electrical specifications..................... 32 3.2.4 32 khz oscillator electrical characteristics......... 34 3.3 memories and memory interfaces................................... 34 3.3.1 quadspi ac specifications............................... 34 3.3.2 flash electrical specifications............................ 39 3.3.3 flexbus switching specifications....................... 41 3.3.4 sdram controller specifications....................... 43 3.4 security and integrity modules........................................ 46 3.5 analog............................................................................. 46 3.5.1 adc electrical specifications............................. 46 3.5.2 cmp and 6-bit dac electrical specifications..... 50 3.5.3 12-bit dac electrical characteristics................. 52 3.5.4 voltage reference electrical specifications........ 55 3.6 timers.............................................................................. 56 3.7 communication interfaces............................................... 56 3.7.1 emv sim specifications.................................... 57 3.7.2 usb vreg electrical specifications.................. 61 3.7.3 usb dcd electrical specifications.................... 62 3.7.4 dspi switching specifications (limited voltage range)................................................................ 63 3.7.5 dspi switching specifications (full voltage range)................................................................ 64 3.7.6 i2c switching specifications.............................. 66 3.7.7 uart switching specifications.......................... 66 3.7.8 lpuart switching specifications...................... 66 3.7.9 sdhc specifications......................................... 67 3.7.10 i2s switching specifications.............................. 68 3.8 human-machine interfaces (hmi).................................... 74 3.8.1 tsi electrical specifications............................... 74 4 dimensions............................................................................. 74 4.1 obtaining package dimensions....................................... 74 5 pinout...................................................................................... 75 5.1 k82 signal multiplexing and pin assignments................. 75 5.2 recommended connection for unused analog and digital pins........................................................................ 82 5.3 k82 pinouts..................................................................... 84 6 ordering parts......................................................................... 88 6.1 determining valid orderable parts.................................... 88 7 part identification..................................................................... 89 7.1 description....................................................................... 89 7.2 format............................................................................. 89 7.3 fields............................................................................... 89 7.4 example........................................................................... 90 8 terminology and guidelines.................................................... 90 8.1 definitions........................................................................ 90 8.2 examples......................................................................... 91 8.3 typical-value conditions.................................................. 91 8.4 relationship between ratings and operating requirements.................................................................... 92 8.5 guidelines for ratings and operating requirements.......... 92 9 revision history...................................................................... 92 4 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current operating ratings ratings kinetis k82 sub-family, rev. 2, 11/2016 5 nxp semiconductors symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v ddio_e v ddio_e is an independent voltage supply for porte 1 C0.3 3.8 v v bat rtc supply voltage C0.3 3.8 v i dd digital supply current 300 ma v io input voltage (except porte, vbat domain pins, and usb0) 2 C0.3 v dd + 0.3 v v io_e porte input voltage 3 C0.3 v ddio_e + 0.3 v i d maximum current single pin limit (digital output pins) C25 25 ma vregin usb regulator input C0.3 6.0 v v usb0_dx usb0_dp and usb_dm input voltage C0.3 3.63 v 1. v ddio_e is independent of the v dd domain and can operate at a voltage independent of v dd . however, it is required that the v dd domain be powered up before v ddio_e . v ddio_e must never be higher than v dd during power ramp up, or power down. v dd and v ddio_e may ramp together if tied to the same power supply. 2. includes adc, cmp, and reset_b inputs. 3. porte analog input voltages cannot exceed v ddio_e supply when v dd v ddio_e . porte analog input voltages cannot exceed v dd supply when v dd < v ddio_e . 1.4.1 recommended por sequencing cases ? vdd = vddio_e ? vdd > vddio_e ? vdd < vddio_e ratings 6 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors figure 2. vdd = vddio_e figure 3. vdd > vddio_e ratings kinetis k82 sub-family, rev. 2, 11/2016 7 nxp semiconductors figure 4. vdd < vddio_e 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 5. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins general 8 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors ? have c l =15pf loads, ? are slew rate disabled, and ? are normal drive strength 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v ddio_e supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v ih_e input high voltage ? 2.7 v v ddio_e 3.6 v ? 1.7 v v ddio_e 2.7 v 0.7 v ddio_e 0.75 v ddio_e v v v il_e input low voltage ? 2.7 v v ddio_e 3.6 v ? 1.7 v v ddio_e 2.7 v 0.35 v ddio_e 0.3 v ddio_e v v v hys input hysteresis 0.06 v dd v v hys_e input hysteresis 0.06 v ddio_e v i icio i/o pin negative dc injection current single pin ? v in < v ss -0.3v -5 ma 1 table continues on the next page... general kinetis k82 sub-family, rev. 2, 11/2016 9 nxp semiconductors table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection -25 ma v odpu pseudo open drain pullup voltage level v dd v dd v 2 v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd or v ddio_e . if v in is less than -0.3v, a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(-0.3-v in )/|i icio |. the actual resistor value should be an order of magnitude higher to tolerate transient voltages. 2. open drain outputs must be pulled to vdd. 2.2.2 hvd, lvd and por operating requirements table 2. v dd supply hvd, lvd and por operating requirements symbol description min. typ. max. unit notes v hvdh high voltage detect (high trip point) 3.72 v v hvdl high voltage detect (low trip point) 3.46 v v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv table continues on the next page... general 10 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 2. v dd supply hvd, lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising threshold is the sum of falling threshold and hysteresis voltage note there is no lvd circuit for vddio domain table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 2.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. typ. 1 max. unit notes v oh output high voltage normal drive strength io group 1 ? 2.7 v v bat 3.6 v, i oh = -5ma ? 1.71 v v bat 2.7 v, i oh = -2.5ma io groups 2 and 3 ? 2.7 v v dd 3.6 v, i oh = -10ma ? 1.71 v v dd 2.7 v, i oh = -5ma io group 4 ? 2.7 v v ddio_e 3.6 v, i oh = -5ma ? 1.71 v v ddio_e 2.7 v, i oh = -2.5ma v bat C 0.5 v bat C 0.5 v dd C 0.5 v dd C 0.5 v ddio_e C 0.5 v ddio_e C 0.5 v v v v v v 2 , 3 output high voltage high drive strength io group 3 ? 2.7 v v dd 3.6 v, i oh = -20ma ? 1.71 v v dd 2.7 v, i oh = -10ma io group 4 ? 2.7 v v ddio_e 3.6 v, i oh = -15ma ? 1.71 v v ddio_e 2.7 v, i oh = -7.5ma v dd C 0.5 v dd C 0.5 v ddio_e C 0.5 v ddio_e C 0.5 v v v v 2 i oht output high current total for all ports 100 ma v ol output low voltage normal drive strength io group 1 2 , 4 , 5 table continues on the next page... general kinetis k82 sub-family, rev. 2, 11/2016 11 nxp semiconductors table 4. voltage and current operating behaviors (continued) symbol description min. typ. 1 max. unit notes ? 2.7 v v bat 3.6 v, i ol = -5ma ? 1.71 v v bat 2.7 v, i ol = -2.5ma io groups 2 and 3 ? 2.7 v v dd 3.6 v, i ol = -10ma ? 1.71 v v dd 2.7 v, i ol = -5ma io group 4 ? 2.7 v v ddio_e 3.6 v, i ol = -5ma ? 1.71 v v ddio_e 2.7 v, i ol = -2.5ma 0.5 0.5 0.5 0.5 0.5 0.5 v v v v v v output low voltage high drive strength io group 3 ? 2.7 v v dd 3.6 v, i ol = -20ma ? 1.71 v v dd 2.7 v, i ol = -10ma io group 4 ? 2.7 v v ddio_e 3.6 v, i ol = -15ma ? 1.71 v v ddio_e 2.7 v, i ol = -7.5ma 0.5 0.5 0.5 0.5 v v v v 2 , 4 i olt output low current total for all ports 100 ma i in input leakage current v dd domain pins ? v ss v in v dd porte pins ? v ss v in v ddio_e v bat domain pins ? v ss v in v bat 0.002 0.002 0.002 0.5 0.5 0.5 a a a 6 , 7 , 8 r pu internal pullup resistors 20 50 k? 9 r pd internal pulldown resistors 20 50 k? 10 1. typical values characterized at 25c and v dd = 3.6v unless otherwise noted. 2. io group 1 includes v bat domain pins: rtc_wakeup_b. io group 2 includes v dd domain pins: porta, portb, portc, and portd, except pta4. io group 3 includes v dd domain pins: ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7. io group 4 includes v ddio_e domain pins: porte. 3. pta4 has lower drive strength: i oh = -5ma for high v dd range; i oh = -2.5ma for low v dd range. 4. open drain outputs must be pulled to v dd . 5. pta4 has lower drive strength: i ol = 5ma for high v dd range; i ol = 2.5ma for low v dd range. 6. v dd domain pins include adc, cmp, and reset_b inputs. measured at v dd = 3.6v. 7. porte analog input voltages cannot exceed v ddio_e supply when v dd v ddio_e . porte analog input voltages cannot exceed v dd supply when v dd ? v ddio_e . 8. v bat domain pins include extal32, xtal32, and rtc_wakeup_b pins. 9. measured at minimum supply voltage and v in = v ss 10. measured at minimum supply voltage and v in = v dd general 12 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx C> run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100mhz ? bus clock = 50mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz ? mcg mode=fei table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s ? vlls0 C> run 154 s ? vlls1 C> run 154 s ? vlls2 C> run 92 s ? vlls3 C> run 92 s ? lls2 C> run 6.3 s ? lls3 C> run 6.3 s ? vlps C> run 5.3 s ? stop C> run 5.3 s table 6. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32kh z 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a table continues on the next page... general kinetis k82 sub-family, rev. 2, 11/2016 13 nxp semiconductors table 6. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i erefsten4mh z external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32k hz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls2 lls3 vlps stop 440 440 490 490 510 510 490 490 490 490 560 560 540 540 540 540 560 560 560 560 560 560 560 560 570 570 570 570 610 610 580 580 680 680 680 680 na i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 234 66 246 66 254 66 260 66 268 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a general 14 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 2.2.5 power consumption operating behaviors the maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). table 7. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from internal flash @ 3.0v ? @ 25c ? @ 105c 28 39.6 31.55 50.10 ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from internal flash @ 3.0v ? @ 25c ? @ 105c 43.30 57.80 46.85 68.30 ma 3 , 4 i dd_runco run mode current in compute operation - 120 mhz core / 24 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0 v ? @ 25c ? @ 105c 25.1 37.8 28.65 48.30 ma 5 i dd_hsrun run mode current all peripheral clocks disabled, code executing from internal flash @ 3.0v ? @ 25c ? @ 105c 38 51.7 40.70 65.04 ma 6 i dd_hsrun run mode current all peripheral clocks enabled, code executing from internal flash @ 3.0v ? @ 25c ? @ 105c 48 63.7 50.70 77.04 ma 7 , 8 i dd_hsrunco hsrun mode current in compute operation C 150 mhz core/ 25 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0v ? @ 25c ? @ 105c 34.5 50.3 37.2 63.64 ma i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 105c 14.2 26.2 19.87 35.66 ma 9 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks enabled 24.4 30.07 ma 9 table continues on the next page... general kinetis k82 sub-family, rev. 2, 11/2016 15 nxp semiconductors table 7. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? @ 25c ? @ 105c 36.6 46.06 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 105c 0.94 3.99 1.10 7.62 ma 10 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled ? @ 25c ? @ 105c 1.36 4.4 1.52 8.03 ma 11 i dd_vlprco_ cm very-low-power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, lptmr running with 4 mhz internal reference clock, coremark benchmark code executing from internal flash at 3.0 v ? @ 25c ? @ 105c 1000 3650 a 12 i dd_pstop2 stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 mhz bus at 3.0 v ? @ 25c ? @ 105c 3.95 17.71 5.75 27.15 ma 5 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 105c 0.45 3.28 0.63 6.87 ma 13 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks enabled ? @ 25c ? @ 105c 0.75 3.6 0.93 7.19 ma i dd_stop stop mode current at 3.0 v ? @ 25c ? @ 105c 0.55 5.67 0.85 9.59 ma i dd_vlps very-low-power stop mode current at 3.0 v ? @ 25c ? @ 105c 91.48 1798.38 240.90 3796.94 a i dd_lls2 low leakage stop mode current at 3.0 v ? @ 25c ? @ 105c 4.94 73.68 7.14 121.9 a table continues on the next page... general 16 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 7. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_lls3 low leakage stop mode current at 3.0 v ? @ 25c ? @ 105c 7.78 160.91 13.16 284.31 a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ 25c ? @ 105c 5.63 117.89 9.34 202.55 a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ 25c ? @ 105c 3.13 29.49 4.04 48.7 a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ 25c ? @ 105c 1.05 15.31 1.36 18.56 a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled ? @ 25c ? @ 105c 0.62 13.92 0.84 16.95 a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled ? @ 25c ? @ 105c 0.33 13.42 0.53 16.44 a i dd_vbat average current with rtc and 32khz disabled at 3.0 v ? @ 25c ? @ 105c 0.19 2.56 0.23 3.71 a i dd_vbat average current when cpu is not accessing rtc registers @ 1.8v ? @ 25c ? @ 105c 0.57 2.52 0.64 5.82 a 14 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. 120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configure for pee mode. all peripheral clocks enabled. 4. max values are measured with cpu executing dsp instructions. 5. mcg configured for pee mode. 6. 150 mhz core and system clock, 50 mhz bus and flexbus clock, and 25 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. general kinetis k82 sub-family, rev. 2, 11/2016 17 nxp semiconductors 7. 150 mhz core and system clock, 50 mhz bus and flexbus clock, and 25 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled. 8. max values are measured with cpu executing dsp instructions. 9. 120 mhz core and system clock, 60mhz bus clock, and flexbus. mcg configured for pee mode. 10. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 11. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 12. mcg configured for blpi mode. coremark benchmark compiled using iar 6.40 with optimization level high, optimized for balanced. 13. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 14. includes 32khz oscillator current and rtc operation. 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfe ? v dd =v dda =v ddio_e general 18 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors figure 6. run mode supply current vs. core frequency general kinetis k82 sub-family, rev. 2, 11/2016 19 nxp semiconductors figure 7. vlpr mode supply current vs. core frequency 2.2.6 electromagnetic compatibility (emc) specifications emc measurements to ic-level iec standards are available from nxp on request. 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: ? go to www.nxp.com . ? perform a keyword search for emc design. general 20 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 2.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes high speed run mode f sys system and core clock 150 mhz normal run mode (and high speed run mode unless otherwise specified above) f sys system and core clock 120 mhz system and core clock when full speed usb in operation 20 mhz f bus bus clock 75 mhz fb_clk flexbus clock 75 mhz f flash flash clock 28 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f flexcan_erclk flexcan external reference clock 8 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. general kinetis k82 sub-family, rev. 2, 11/2016 21 nxp semiconductors 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, cmt, timers, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 nmi_b pin interrupt pulse width (analog filter enabled) asynchronous path 100 ns gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 50 ns 3 external reset_b input pulse width (digital glitch filter disabled) 100 ns port rise and fall time (high drive strength) ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 34 16 10 8 ns ns ns ns 4 , 5 port rise and fall time (low drive strength) ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 34 16 7 5 ns ns ns ns 6 , 7 port rise and fall time (high drive strength) ? slew enabled ? 1.71 v ddio_e 2.7v ? 2.7 v ddio_e 3.6v ? slew disabled ? 1.71 v ddio_e 2.7v ? 2.7 v ddio_e 3.6v 34 16 7 5 ns ns ns ns 5 , 8 port rise and fall time (low drive strength) ? slew enabled 34 16 ns ns 7 , 8 general 22 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 10. general switching specifications symbol description min. max. unit notes ? 1.71 v ddio_e 2.7v ? 2.7 v ddio_e 3.6v ? slew disabled ? 1.71 v ddio_e 2.7v ? 2.7 v ddio_e 3.6v 7 5 ns ns 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7. 5. 75 pf load. 6. ports a, b, c, and d. 7. 25 pf load. 8. port e pins only. 2.4 thermal specifications 2.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 , 1. maximum t a can be exceeded only if the user ensures that t j does not exceed the maximum. the simplest method to determine t j is: t j = t a + r ja x chip power dissipation 2.4.2 thermal attributes table 12. thermal attributes board type symbol description 100 lqfp 121 xfbga unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 52 71 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 39 36.8 c/w 1 table continues on the next page... general kinetis k82 sub-family, rev. 2, 11/2016 23 nxp semiconductors table 12. thermal attributes (continued) board type symbol description 100 lqfp 121 xfbga unit notes single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 42 55 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 33 32.2 c/w 1 r jb thermal resistance, junction to board 24 18 c/w 2 r jc thermal resistance, junction to case 11 12.2 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 0.25 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. board meets jesd51-9 specification. 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 debug trace timing specifications table 13. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 1.5 ns t h data hold 1.0 ns peripheral operating requirements and behaviors 24 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors traceclk t r t wh t f t cyc t wl figure 8. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 9. trace data specifications 3.1.2 jtag electricals table 14. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 28 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 25 nxp semiconductors table 14. jtag limited voltage range electricals (continued) symbol description min. max. unit j11 tclk low to tdo data valid 19 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 15. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 30.6 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.0 ns j11 tclk low to tdo data valid 19.0 ns j12 tclk low to tdo high-z 17.0 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 10. test clock input timing peripheral operating requirements and behaviors 26 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 11. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 12. test access port timing peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 27 nxp semiconductors j14 j13 tclk trst figure 13. trst timing 3.2 clock modules 3.2.1 mcg specifications table 16. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz i ints internal reference (slow clock) current 20 a t irefsts [o: ] internal reference (slow clock) startup time 32 s f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature 1 2 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.5 1 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz i intf internal reference (fast clock) current 25 a t irefsts [l: ] internal reference startup time (fast clock) 10 15 s f loc_low loss of external clock minimum frequency range = 00 ext clk freq: above (3/5)f int never reset (3/5) x f ints_t khz table continues on the next page... peripheral operating requirements and behaviors 28 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 16. mcg specifications (continued) symbol description min. typ. max. unit notes ext clk freq: between (2/5)fint and (3/5)f int maybe reset (phase dependency) ext clk freq: below (2/5)f int always reset f loc_high loss of external clock minimum frequency range = 01, 10, or 11 ext clk freq: above (16/5)f int never reset ext clk freq: between (15/5)f int and (16/5)f int maybe reset (phase dependency) ext clk freq: below (15/5)f int always reset (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco_ut dco output frequency range untrimmed low range (drs=00, dmx32=0) 640 f ints_ut 16.0 23.04 26.66 mhz 2 mid range (drs=01, dmx32=0) 1280 f ints_ut 32.0 46.08 53.32 mid-high range (drs=10, dmx32=0) 1920 f ints_ut 48.0 69.12 79.99 high range (drs=11, dmx32=0) 2560 f ints_ut 64.0 92.16 106.65 low range (drs=00, dmx32=1) 732 f ints_ut 18.3 26.35 30.50 mid range (drs=01, dmx32=1) 1464 f ints_ut 36.6 52.70 60.99 mid-high range (drs=10, dmx32=1) 2197 f ints_ut 54.93 79.09 91.53 high range (drs=11, dmx32=1) 2929 f ints_ut 73.23 105.44 122.02 f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs=01) 40 41.94 50 mhz table continues on the next page... peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 29 nxp semiconductors table 16. mcg specifications (continued) symbol description min. typ. max. unit notes 1280 f fll_ref mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f dco = 48 mhz ? f dco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 7 pll f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 180 360 mhz f vcoclk pll output frequency 90 180 mhz f vcoclk_90 pll quadrature output frequency 90 180 mhz i pll pll operating current ? vco @ 176 mhz (f pll_ref = 8 mhz, vdiv multiplier = 22, prdiv divide=1) 1.1 ma 8 i pll pll operating current ? vco @ 360 mhz (f pll_ref = 8 mhz, vdiv multiplier = 45, prdiv divide=1) 2 ma 8 j cyc_pll pll period jitter (rms) ? f vco = 180 mhz ? f vco = 360 mhz 100 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 180 mhz ? f vco = 360 mhz 600 300 ps ps 9 d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 10 peripheral operating requirements and behaviors 30 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. this applies when sctrim at value (0x80) and scftrim control bit at value (0x0). 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. excludes any oscillator currents that are also consuming power while pll is in operation. 9. this specification was obtained using a nxp developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.2.2 irc48m specifications table 17. irc48m specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i dd48m supply current 520 a f irc48m internal reference frequency 48 mhz f irc48m_ol_lv open loop total deviation of irc48m frequency at low voltage (vdd=1.71v-1.89v) over temperature ? regulator disable (usb_clk_recover_irc_en[reg_en]=0) ? regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.5 0.5 1.0 1.5 %f irc48m f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over temperature ? regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.5 1.0 %f irc48m f irc48m_cl closed loop total deviation of irc48m frequency over voltage and temperature 0.1 %f host 1 j cyc_irc48m period jitter (rms) 35 150 ps t irc48mst startup time 2 3 s 2 1. closed loop operation of the irc48m is only feasible for usb device operation; it is not usable for usb host operation. it is enabled by configuring for usb device, selecting irc48m as usb clock source, and enabling the clock recover function (usb_clk_recover_irc_ctrl[clock_recover_en]=1, usb_clk_recover_irc_en[irc_en]=1). 2. irc48m startup time is defined as the time between clock enablement and clock availability for system use. enable the clock by one of the following settings: ? usb_clk_recover_irc_en[irc_en]=1, or ? mcg_c7[oscsel]=10, or ? sim_sopt2[pllfllsel]=11 peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 31 nxp semiconductors 3.2.3 oscillator electrical specifications 3.2.3.1 oscillator dc electrical specifications table 18. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 600 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 7.5 500 650 2.5 3.25 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) table continues on the next page... peripheral operating requirements and behaviors 32 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 18. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c, internal capacitance = 20 pf 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.3.2 oscillator frequency specifications table 19. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high-frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 1 , 2 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. proper pc board layout procedures must be followed to achieve specifications. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 33 nxp semiconductors 2. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.2.4 32 khz oscillator electrical characteristics 3.2.4.1 32 khz oscillator dc electrical specifications table 20. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.4.2 32 khz oscillator frequency specifications table 21. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 3.3 memories and memory interfaces peripheral operating requirements and behaviors 34 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3.3.1 quadspi ac specifications ? all data is based on a negative edge data launch from the device and a positive edge data capture, as shown in the timing diagrams in this section. ? measurements are with a load of 15pf (1.8v) and 35pf (3v) on output pins. input slew: 1ns ? timings assume a setting of 0x0000_000x for quadspi _smpr register (see the reference manual for details). the following table lists the quadspi delay chain read/write settings. refer the device reference manual for register and bit descriptions. table 22. quadspi delay chain read/write settings mode quadspi registers notes quadspi_mcr[dq s_en] quadspi_soccr[ soccfg] quadspi_mcr[sc lkcfg] quadspi_flshc r[tdh] sdr yes 3fh 5 no delay of 63 buffer and 64 mux ddr yes 3fh 1 2 delay of 63 buffer and 64 mux hyperflash rds driven from flash 0h no 2 delay of 1 mux sdr mode 1 2 3 tck tcss tcsh tis tih clock sfck cs data in figure 14. quadspi input timing (sdr mode) diagram note ? the below timing values are with default settings for sampling registers like quadspi_smpr. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 35 nxp semiconductors ? a negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. ? the below timing are for a load of 15pf (1.8v) and 35pf (3v) or output pads ? all board delays need to be added appropriately ? input hold time being negative does not have any implication or max achievable frequency table 23. quadspi input timing (sdr mode) specifications symbol parameter value unit min max t is setup time for incoming data 4 - ns t ih hold time requirement for incoming data 1.5 - ns 1 2 3 toh tov tck tcss tcsh clock sfck cs data out figure 15. quadspi output timing (sdr mode) diagram table 24. quadspi output timing (sdr mode) specifications symbol parameter value unit min max t ov output data valid - 2.8 ns t oh output data hold -1.4 - ns t ck sck clock period - 100 mhz t css chip select output setup time 2 - ns t csh chip select output hold time -1 - ns note for any frequency setup and hold specifications of the memory should be met. peripheral operating requirements and behaviors 36 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors ddr mode 1 2 3 tck tcss tcsh tis tih clock sfck cs data in figure 16. quadspi input timing (ddr mode) diagram note ? numbers are for a load of 15pf (1.8v) and 35pf (3v) ? the numbers are for setting of hold condition in register quadspi_smpr[ddrsnp] table 25. quadspi input timing (ddr mode) specifications symbol parameter value unit min max t is setup time for incoming data 4 (without learning) - ns 1 (with learning) t ih hold time requirement for incoming data 1.5 - ns 1 2 3 tck tcss tcsh tov toh clock sfck cs data out figure 17. quadspi output timing (ddr mode) diagram peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 37 nxp semiconductors table 26. quadspi output timing (ddr mode) specifications symbol parameter value unit min max t ov output data valid - 4.5 ns t oh output data hold 1.5 - ns t ck sck clock period - 75 (with learning) mhz - 45 (without learning) t css chip select output setup time 2 - clk(sck) t csh chip select output hold time -1 - clk(sck) hyperflash mode ts min rds di[7:0] th min figure 18. quadspi input timing (hyperflash mode) diagram table 27. quadspi input timing (hyperflash mode) specifications symbol parameter value unit min max ts min setup time for incoming data 2 - ns th min hold time requirement for incoming data 2 - ns peripheral operating requirements and behaviors 38 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors ck ck 2 t ho t dvo tclk skmax tclk skmin output invalid data figure 19. quadspi output timing (hyperflash mode) diagram table 28. quadspi output timing (hyperflash mode) specifications symbol parameter value unit min max tdv max output data valid - 4.3 ns tho output data hold 1.3 - ns tclk skmax ck to ck2 skew max - t/4 + 0.5 ns tclk skmin ck to ck2 skew min t/4 - 0.5 - ns note maximum clock frequency = 75 mhz. 3.3.2 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 3.3.2.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 29. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s table continues on the next page... peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 39 nxp semiconductors table 29. nvm program/erase timing specifications (continued) symbol description min. typ. max. unit notes t hversscr sector erase high-voltage time 13 113 ms 1 t hversall erase all high-voltage time 208 1808 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.3.2.2 flash timing specifications commands table 30. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec4k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 0.9 ms 1 t rdonce read once execution time 30 s 1 t pgmonce program once execution time 100 s t ersall erase all blocks execution time 280 2100 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.3.2.3 flash high voltage current behaviors table 31. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.3.2.4 reliability specifications table 32. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years table continues on the next page... peripheral operating requirements and behaviors 40 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 32. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at C40 c t j c. 3.3.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 33. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 11.8 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 6 ns fb5 data and fb_ta input hold 0.0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. table 34. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 12.6 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 41 nxp semiconductors table 34. flexbus full voltage range switching specifications (continued) num description min. max. unit notes fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 12.5 ns fb5 data and fb_ta input hold 0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 read timing parameters electricals_read.svg s0 s1 s2 s3 s0 s0 s1 s2 s3 s0 figure 20. flexbus read timing diagram peripheral operating requirements and behaviors 42 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] write timing parameters electricals_write.svg figure 21. flexbus write timing diagram 3.3.4 sdram controller specifications the figure below shows sdram read cycle. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 43 nxp semiconductors a[23:0] sras d[31:0] actv nop sdram_cs [1:0] read column clkout 0 dramw bs [3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 d1 d2 d4 d6 d5 d4 1 1 nop d4 row d3 pre d0 scas dacr[casl] = 2 figure 22. sdram read timing diagram table 35. sdram timing (full voltage range) num characteristic 1 symbol min max unit operating voltage 1.71 3.6 v frequency of operation clkout mhz d0 clock period 1/clkout ns 2 d1 clkout high to sdram address valid t chdav - 11.2 ns d2 clkout high to sdram control valid t chdcv 11.1 ns d3 clkout high to sdram address invalid t chdai 1.0 - ns d4 clkout high to sdram control invalid t chdci 1.0 - ns d5 sdram data valid to clkout high t ddvch 12.0 - ns d6 clkout high to sdram data invalid t chddi 1.0 - ns d7 3 clkout high to sdram data valid t chddvw - 12.0 ns d8 3 clkout high to sdram data invalid t chddiw 1.0 - ns 1. all timing specifications are based on taking into account, a 25pf load on the sdram output pins. 2. clkout is same as fb_clk, maximum frequency can be 75 mhz peripheral operating requirements and behaviors 44 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3. d7 and d8 are for write cycles only. table 36. sdram timing (limited voltage range) num characteristic 1 symbol min max unit operating voltage 2.7 3.6 v frequency of operation clkout mhz d0 clock period 1/clkout ns 2 d1 clkout high to sdram address valid t chdav - 11.1 ns d2 clkout high to sdram control valid t chdcv 11.1 ns d3 clkout high to sdram address invalid t chdai 1.0 - ns d4 clkout high to sdram control invalid t chdci 1.0 - ns d5 sdram data valid to clkout high t ddvch 7.3 - ns d6 clkout high to sdram data invalid t chddi 1.0 - ns d7 3 clkout high to sdram data valid t chddvw - 11.1 ns d8 3 clkout high to sdram data invalid t chddiw 1.0 - ns 1. all timing specifications are based on taking into account, a 25pf load on the sdram output pins. 2. clkout is same as fb_clk, maximum frequency can be 75 mhz 3. d7 and d8 are for write cycles only. following figure shows an sdram write cycle. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 45 nxp semiconductors a[23:0] sras scas 1 d[31:0] actv pallnop sdram_cs [1:0] write row column clkout dramw bs [3:0] d1 d2 d4 d8 d4 0 1 2 3 4 5 6 7 8 9 10 11 12 d7 nop 1 dacr[casl] = 2 d4 d3 d2 d4 d0 figure 23. sdram write timing diagram 3.4 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.5 analog 3.5.1 adc electrical specifications the 16-bit accuracy specifications listed in table 37 and table 38 are achievable on the differential pins adcx_dp0, adcx_dm0. peripheral operating requirements and behaviors 46 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.5.1.1 adc operating conditions table 37. adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 vrefh vrefh v c adin input capacitance ? 8-bit / 10-bit / 12-bit modes 4 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 18.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 47 nxp semiconductors r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 24. adc input impedance equivalency diagram 3.5.1.2 adc electrical characteristics table 38. adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes 1.0 C2.7 to +1.9 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors 48 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 38. adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? <12-bit modes 0.5 C0.7 to +0.5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 13-bit modes 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 49 nxp semiconductors 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 25. typical enob vs. adc_clk for 16-bit differential mode 3.5.2 cmp and 6-bit dac electrical specifications table 39. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a table continues on the next page... peripheral operating requirements and behaviors 50 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 39. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 26. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 51 nxp semiconductors 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 27. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.5.3 12-bit dac electrical characteristics 3.5.3.1 12-bit dac operating requirements table 40. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors 52 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3.5.3.2 12-bit dac operating behaviors table 41. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high- speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c a c offset aging coefficient 100 v/yr rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 53 nxp semiconductors 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 28. typical inl error vs. digital code peripheral operating requirements and behaviors 54 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 29. offset at half scale vs. temperature 3.5.4 voltage reference electrical specifications table 42. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 55 nxp semiconductors table 43. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v 1 v out voltage reference output factory trim 1.1584 1.2376 v 1 v out voltage reference output user trim 1.193 1.197 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv 1 i bg bandgap only current 80 a 1 i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = 1.0 ma 200 v 1 , 2 t stup buffer startup time 100 s t chop_osc_st up internal bandgap start-up delay with chop oscillator enabled 35 ms v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 44. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 45. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 3.6 timers see general switching specifications . 3.7 communication interfaces peripheral operating requirements and behaviors 56 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3.7.1 emv sim specifications each emv sim module interface consists of a total of five pins. the interface is designed to be used with synchronous smart cards, meaning the emv sim module provides the clock used by the smart card. the clock frequency is typically 372 times the tx/rx data rate; however, the emv sim module can also work with clk frequencies of 16 times the tx/rx data rate. there is no timing relationship between the clock and the data. the clock that the emv sim module provides to the smart card is used by the smart card to recover the clock from the data in the same manner as standard uart data exchanges. all five signals of the emv sim module are asynchronous with each other. there are no required timing relationships between signals in normal mode. the smart card is initiated by the interface device; the smart card responds with answer to reset. although the emv sim interface has no defined requirements, the iso/iec 7816 defines reset and power-down sequences (for detailed information see iso/iec 7816). emvsimn_pd emvsimn_rst emvsimn_clk emvsimn_io emvsimn_vccen si7 si8 si9 si10 figure 30. emv sim clock timing diagram peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 57 nxp semiconductors the following table defines the general timing requirements for the emv sim interface. table 46. timing specifications, high drive strength id parameter symbol min max unit si 1 emv sim clock frequency (emvsimn_clk) 1 s freq 1 5 mhz si 2 emv sim clock rise time (emvsimn_clk) 2 s rise 0.09 (1/sfreq) ns si 3 emv sim clock fall time (emvsimn_clk) 2 s fall 0.09 (1/sfreq) ns si 4 emv sim input transition time (emvsimn_io, emvsimn_pd) s tran 20 25 ns si 5 emv sim i/o rise time / fall time (emvsimn_io) 3 tr/tf 1 ns si 6 emv sim rst rise time / fall time (emvsimn_rst) 4 tr/tf 1 ns 1. 50% duty cycle clock, 2. with c = 50 pf 3. with cin = 30 pf, cout = 30 pf, 4. with cin = 30 pf, 3.7.1.1 emv sim reset sequences smart cards may have internal reset, or active low reset. the following subset describes the reset sequences in these two cases. 3.7.1.1.1 smart cards with internal reset following figure shows the reset sequence for smart cards with internal reset. the reset sequence comprises the following steps: ? after power-up, the clock signal is enabled on emvsimn_clk (time t0) ? after 200 clock cycles, emvsimn_io must be asserted. ? the card must send a response on emvsimn_io acknowledging the reset between 400C40000 clock cycles after t0. peripheral operating requirements and behaviors 58 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors emvsimn_clk emvsimn_io 2 t0 response 1 emvsimn_vccen figure 31. internal reset card reset sequence the following table defines the general timing requirements for the sim interface. table 47. timing specifications, internal reset card reset sequence ref min max units 1 200 emvsimx_clk clock cycles 2 400 40,000 emvsimx_clk clock cycles 3.7.1.1.2 smart cards with active low reset following figure shows the reset sequence for smart cards with active low reset. the reset sequence comprises the following steps:: ? after power-up, the clock signal is enabled on emvsimn_clk (time t0) ? after 200 clock cycles, emvsimn_io must be asserted. ? emvsimn_rst must remain low for at least 40,000 clock cycles after t0 (no response is to be received on rx during those 40,000 clock cycles) ? emvsimn_rst is asserted (at time t1) ? emvsimn_rst must remain asserted for at least 40,000 clock cycles after t1, and a response must be received on emvsimn_io between 400 and 40,000 clock cycles after t1. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 59 nxp semiconductors emv simn_vccen emvsimn_clk emvsimn_io 2 t0 1 response emvsimn_rst t1 3 3 figure 32. active-low-reset smart card reset sequence the following table defines the general timing requirements for the emvsim interface.. table 48. timing specifications, internal reset card reset sequence ref no min max units 1 200 emvsimx_clk clock cycles 2 400 40,000 emvsimx_clk clock cycles 3 40,000 emvsimx_clk clock cycles 3.7.1.2 emvsim power-down sequence following figure shows the emv sim interface power-down ac timing diagram. table 49 table shows the timing requirements for parameters (si7Csi10) shown in the figure. the power-down sequence for the emv sim interface is as follows: ? emvsimn_simpd port detects the removal of the smart card ? emvsimn_rst is negated ? emvsimn_clk is negated ? emvsim_io is negated ? emvsimx_vcceny is negated each of the above steps requires one frtcclk period (usually 32 khz and selected by sim_sopt1[osc32ksel]). power-down may be initiated by a smart card removal detection; or it may be launched by the processor. peripheral operating requirements and behaviors 60 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors emvsimn_pd emvsimn_rst emvsimn_clk emvsimn_io emvsimn_vccen si7 si8 si9 si10 figure 33. smart card interface power down ac timing table 49. timing requirements for power-down sequence ref no parameter symbol min max units si7 emvsim reset to sim clock stop s rst2clk 0.9 1/ frtcclk 1 1.1 1/frtcclk s si8 emvsim reset to sim tx data low s rst2dat 1.8 1/ frtcclk 2.2 1/frtcclk s si9 emvsim reset to sim voltage enable low s rst2ven 2.7 1/ frtcclk 3.3 1/frtcclk s si10 emvsim presence detect to sim reset low s pd2rst 0.9 1/ frtcclk 1.1 1/frtcclk s 1. frtcclk is erclk32k, and this clock must be enabled during the power down sequence. note same timing is also followed when auto power down is initiated. see reference manual for reference. peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 61 nxp semiconductors 3.7.2 usb vreg electrical specifications table 50. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 125 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 10 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25 c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 3.7.3 usb dcd electrical specifications table 51. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src , v dm_src usb_dp and usb_dm source voltages (up to 250 a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink , i dp_sink usb_dm and usb_dp sink currents 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 0.33 0.4 v peripheral operating requirements and behaviors 62 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3.7.4 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 52. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 15.0 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 15.8 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 34. dspi classic spi timing master mode peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 63 nxp semiconductors table 53. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 1 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 23.0 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.7 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13 ns ds16 dspi_ss inactive to dspi_sout not driven 13 ns 1. the maximum operating frequency is measured with non-continuous cs and sck. when dspi is configured with continuous cs and sck, there is a constraint that spi clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60mhz, spi clock should not be greater than 10mhz. first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 35. dspi classic spi timing slave mode peripheral operating requirements and behaviors 64 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3.7.5 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 54. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 16 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 19.1 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 36. dspi classic spi timing master mode table 55. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v table continues on the next page... peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 65 nxp semiconductors table 55. slave mode dspi timing (full voltage range) (continued) num description min. max. unit frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 23.1 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.6 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13.0 ns ds16 dspi_ss inactive to dspi_sout not driven 13.0 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 37. dspi classic spi timing slave mode 3.7.6 i 2 c switching specifications see general switching specifications . 3.7.7 uart switching specifications see general switching specifications . 3.7.8 lpuart switching specifications see general switching specifications . peripheral operating requirements and behaviors 66 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 3.7.9 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 56. sdhc full voltage range switching specifications num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25/45 mhz fpp clock frequency (mmc full speed\high speed) 0 25/45 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) 0 8.1 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns table 57. sdhc limited voltage range switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\50 mhz fpp clock frequency (mmc full speed\high speed) 0 20\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) 0 7 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) table continues on the next page... peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 67 nxp semiconductors table 57. sdhc limited voltage range switching specifications (continued) num symbol description min. max. unit sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 38. sdhc timing 3.7.10 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 58. i2s master mode timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 80 ns s4 i2s_bclk pulse width high/low 45% 55% bclk period s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid 0 ns table continues on the next page... peripheral operating requirements and behaviors 68 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 58. i2s master mode timing (limited voltage range) (continued) num description min. max. unit s7 i2s_bclk to i2s_txd valid 15 ns s8 i2s_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_fs input setup before i2s_bclk 15 ns s10 i2s_rxd/i2s_fs input hold after i2s_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 39. i 2 s timing master mode table 59. i2s slave mode timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 80 ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 4.5 ns s14 i2s_fs input hold after i2s_bclk 2 ns s15 i2s_bclk to i2s_txd/i2s_fs output valid 20 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ns s17 i2s_rxd setup before i2s_bclk 4.5 ns s18 i2s_rxd hold after i2s_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 69 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd s19 figure 40. i 2 s timing slave modes 3.7.10.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 60. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors 70 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 41. i2s/sai timing master modes table 61. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 23.1 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 71 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 42. i2s/sai timing slave modes 3.7.10.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 62. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors 72 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 43. i2s/sai timing master modes table 63. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 5 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 56.5 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 5 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kinetis k82 sub-family, rev. 2, 11/2016 73 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 44. i2s/sai timing slave modes 3.8 human-machine interfaces (hmi) 3.8.1 tsi electrical specifications table 64. tsi electrical specifications symbol description min. typ. max. unit tsi_runf fixed power consumption in run mode 100 a tsi_runv variable power consumption in run mode (depends on oscillator's current selection) 1.0 128 a tsi_en power consumption in enable mode 100 a tsi_dis power consumption in disable mode 1.2 a tsi_ten tsi analog enable time 66 s tsi_cref tsi reference capacitor 1.0 pf tsi_dvolt voltage variation of vp & vm around nominal values 0.19 1.03 v 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. dimensions 74 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 100-pin lqfp 98ass23308w 121-pin xfbga 98asa00595d 144-pin lqfp 98ass23177w 1 1. the 144-pin lqfp package for this product is not yet available, however it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. 5 pinout 5.1 k82 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. note the 144-pin lqfp and 121-wlcsp packages for this product are not yet available, however they are included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode x h6 k9 nc nc nc g8 adc0_ se16 adc0_ se16 adc0_ se16 a11 nc nc nc j6 nc nc nc j4 nc nc nc 1 1 b1 c10 pte0 disabled pte0 spi1_ pcs1 lpuart1_ tx sdhc0_d1 qspi0a_ data3 i2c1_sda rtc_ clkout 2 2 c2 d9 pte1/ llwu_p0 disabled pte1/ llwu_p0 spi1_sck lpuart1_ rx sdhc0_d0 qspi0a_ sclk i2c1_scl spi1_sin 3 3 c1 d10 pte2/ llwu_p1 disabled pte2/ llwu_p1 spi1_ sout lpuart1_ cts_b sdhc0_ dclk qspi0a_ data0 spi1_sck 4 4 d2 b11 pte3 disabled pte3 spi1_ pcs2 lpuart1_ rts_b sdhc0_ cmd qspi0a_ data2 spi1_ sout pinout kinetis k82 sub-family, rev. 2, 11/2016 75 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode 5 5 f7 f6 vss vss vss 6 6 e5 f7 vddio_e vddio_e vddio_e 7 7 d1 c11 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_sin lpuart3_ tx sdhc0_d3 qspi0a_ data1 8 8 e2 e8 pte5 disabled pte5 spi1_ pcs0 lpuart3_ rx sdhc0_d2 qspi0a_ ss0_b ftm3_ch0 usb0_ sof_out 9 9 e1 e9 pte6/ llwu_p16 disabled pte6/ llwu_p16 spi1_ pcs3 lpuart3_ cts_b i2s0_ mclk qspi0b_ data3 ftm3_ch1 sdhc0_d4 10 10 f3 e10 pte7 disabled pte7 spi2_sck lpuart3_ rts_b i2s0_rxd0 qspi0b_ sclk ftm3_ch2 qspi0a_ ss1_b 11 11 f2 d11 pte8 disabled pte8 i2s0_rxd1 spi2_ sout i2s0_rx_ fs qspi0b_ data0 ftm3_ch3 sdhc0_d5 12 12 f1 e11 pte9/ llwu_p17 disabled pte9/ llwu_p17 i2s0_txd1 spi2_ pcs1 i2s0_rx_ bclk qspi0b_ data2 ftm3_ch4 sdhc0_d6 13 13 g2 f8 pte10/ llwu_p18 disabled pte10/ llwu_p18 i2c3_sda spi2_sin i2s0_txd0 qspi0b_ data1 ftm3_ch5 sdhc0_d7 14 14 g1 f9 pte11 disabled pte11 i2c3_scl spi2_ pcs0 i2s0_tx_ fs qspi0b_ ss0_b ftm3_ch6 qspi0a_ dqs 15 pte12 disabled pte12 lpuart2_ tx i2s0_tx_ bclk qspi0b_ dqs ftm3_ch7 fxio0_d2 qspi0a_ data3 16 pte13 disabled pte13 lpuart2_ rx qspi0b_ ss1_b sdhc0_ clkin fxio0_d3 qspi0a_ sclk 17 15 f10 vddio_e vddio_e vddio_e 18 16 f11 vss vss vss 19 pte16 adc0_ se4a adc0_ se4a pte16 spi0_ pcs0 lpuart2_ tx ftm_ clkin0 ftm0_ flt3 fxio0_d4 qspi0a_ data0 20 pte17/ llwu_p19 adc0_ se5a adc0_ se5a pte17/ llwu_p19 spi0_sck lpuart2_ rx ftm_ clkin1 lptmr0_ alt3/ lptmr1_ alt3 fxio0_d5 qspi0a_ data2 21 pte18/ llwu_p20 adc0_ se6a adc0_ se6a pte18/ llwu_p20 spi0_ sout lpuart2_ cts_b i2c0_sda fxio0_d6 qspi0a_ data1 22 pte19 adc0_ se7a adc0_ se7a pte19 spi0_sin lpuart2_ rts_b i2c0_scl fxio0_d7 qspi0a_ ss0_b 23 16 h3 f11 vss vss vss 24 17 h2 g11 usb0_dp usb0_dp usb0_dp 25 18 h1 h11 usb0_dm usb0_dm usb0_dm 26 19 j1 g10 vout33 vout33 vout33 27 20 j2 h10 vregin vregin vregin 28 21 g9 nc nc nc 29 k2 j10 adc0_dp0 adc0_dp0 adc0_dp0 30 k1 k10 adc0_ dm0 adc0_ dm0 adc0_ dm0 31 j3 j11 adc0_dp3 adc0_dp3 adc0_dp3 pinout 76 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode 32 k3 k11 adc0_ dm3 adc0_ dm3 adc0_ dm3 33 22 f5 h8 vdda vdda vdda 34 23 g5 h9 vrefh vrefh vrefh 35 24 g6 j9 vrefl vrefl vrefl 36 25 f6 j8 vssa vssa vssa 37 26 l2 adc0_dp1 adc0_dp1 adc0_dp1 38 27 l1 adc0_ dm1 adc0_ dm1 adc0_ dm1 39 28 l3 l11 vref_ out/ cmp1_in5/ cmp0_in5/ adc0_ se22 vref_ out/ cmp1_in5/ cmp0_in5/ adc0_ se22 vref_ out/ cmp1_in5/ cmp0_in5/ adc0_ se22 40 29 k4 l10 dac0_ out/ cmp1_in3/ adc0_ se23 dac0_ out/ cmp1_in3/ adc0_ se23 dac0_ out/ cmp1_in3/ adc0_ se23 42 30 k5 h7 rtc_ wakeup_ b rtc_ wakeup_ b rtc_ wakeup_ b 43 31 l4 l9 xtal32 xtal32 xtal32 44 32 l5 l8 extal32 extal32 extal32 45 33 k6 k8 vbat vbat vbat 46 34 g7 vdd vdd vdd 47 35 f6 vss vss vss 48 h5 l7 pta20 disabled pta20 i2c0_scl lpuart4_ tx ftm_ clkin1 fxio0_d8 ewm_ out_b tpm_ clkin1 49 j5 k7 pta21/ llwu_p21 disabled pta21/ llwu_p21 i2c0_sda lpuart4_ rx fxio0_d9 ewm_in 50 36 l7 j7 pta0 jtag_ tclk/ swd_clk tsi0_ch1 pta0 lpuart0_ cts_b ftm0_ch5 fxio0_d10 emvsim0_ clk jtag_ tclk/ swd_clk 51 37 h8 j6 pta1 jtag_tdi tsi0_ch2 pta1 lpuart0_ rx ftm0_ch6 i2c3_sda fxio0_d11 emvsim0_ io jtag_tdi 52 38 j7 k6 pta2 jtag_ tdo/ trace_ swo tsi0_ch3 pta2 lpuart0_ tx ftm0_ch7 i2c3_scl fxio0_d12 emvsim0_ pd jtag_ tdo/ trace_ swo 53 39 h9 l6 pta3 jtag_ tms/ swd_dio tsi0_ch4 pta3 lpuart0_ rts_b ftm0_ch0 fxio0_d13 emvsim0_ rst jtag_ tms/ swd_dio 54 40 j8 h6 pta4/ llwu_p3 nmi_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 fxio0_d14 emvsim0_ vccen nmi_b pinout kinetis k82 sub-family, rev. 2, 11/2016 77 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode 55 41 k7 h5 pta5 disabled pta5 usb0_ clkin ftm0_ch2 fxio0_d15 i2s0_tx_ bclk jtag_ trst_b 56 l10 g6 vdd vdd vdd 57 k10 f5 vss vss vss 58 pta6 disabled pta6 i2c2_scl ftm0_ch3 emvsim1_ clk clkout trace_ clkout 59 pta7 adc0_ se10 adc0_ se10 pta7 i2c2_sda ftm0_ch4 emvsim1_ io trace_d3 60 pta8 adc0_ se11 adc0_ se11 pta8 ftm1_ch0 emvsim1_ pd ftm1_qd_ pha/ tpm1_ch0 trace_d2 61 pta9 disabled pta9 ftm1_ch1 emvsim1_ rst ftm1_qd_ phb/ tpm1_ch1 trace_d1 62 j9 l5 pta10/ llwu_p22 disabled pta10/ llwu_p22 i2c2_sda ftm2_ch0 emvsim1_ vccen fxio0_d16 ftm2_qd_ pha/ tpm2_ch0 trace_d0 63 h7 l4 pta11/ llwu_p23 disabled pta11/ llwu_p23 i2c2_scl ftm2_ch1 fxio0_d17 ftm2_qd_ phb/ tpm2_ch1 64 42 k8 k5 pta12 disabled pta12 ftm1_ch0 trace_ clkout fxio0_d18 i2s0_txd0 ftm1_qd_ pha/ tpm1_ch0 65 43 l8 j5 pta13/ llwu_p4 disabled pta13/ llwu_p4 ftm1_ch1 trace_d3 fxio0_d19 i2s0_tx_ fs ftm1_qd_ phb/ tpm1_ch1 66 44 k9 l3 pta14 disabled pta14 spi0_ pcs0 lpuart0_ tx trace_d2 fxio0_d20 i2s0_rx_ bclk i2s0_txd1 67 45 l9 k4 pta15 disabled pta15 spi0_sck lpuart0_ rx trace_d1 fxio0_d21 i2s0_rxd0 68 46 j10 j4 pta16 disabled pta16 spi0_ sout lpuart0_ cts_b trace_d0 fxio0_d22 i2s0_rx_ fs i2s0_rxd1 69 47 h10 k3 pta17 disabled pta17 spi0_sin lpuart0_ rts_b fxio0_d23 i2s0_ mclk 70 48 e6 l2 vdd vdd vdd 71 49 g7 k2 vss vss vss 72 50 l11 l1 pta18 extal0 extal0 pta18 ftm0_ flt2 ftm_ clkin0 tpm_ clkin0 73 51 k11 k1 pta19 xtal0 xtal0 pta19 ftm1_ flt0 ftm_ clkin1 lptmr0_ alt1/ lptmr1_ alt1 tpm_ clkin1 74 52 j11 j1 reset_b reset_b reset_b 75 pta24 disabled pta24 emvsim0_ clk fb_a29 pinout 78 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode 76 pta25 disabled pta25 emvsim0_ io fb_a28 77 pta26 disabled pta26 emvsim0_ pd fb_a27 78 pta27 disabled pta27 emvsim0_ rst fb_a26 79 pta28 disabled pta28 emvsim0_ vccen fb_a25 80 h11 j2 pta29 disabled pta29 fb_a24 81 53 g11 j3 ptb0/ llwu_p5 adc0_ se8/ tsi0_ch0 adc0_ se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 sdram_ cas_b ftm1_qd_ pha/ tpm1_ch0 fxio0_d0 82 54 g10 h2 ptb1 adc0_ se9/ tsi0_ch6 adc0_ se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 sdram_ ras_b ftm1_qd_ phb/ tpm1_ch1 fxio0_d1 83 55 g9 h1 ptb2 adc0_ se12/ tsi0_ch7 adc0_ se12/ tsi0_ch7 ptb2 i2c0_scl lpuart0_ rts_b sdram_ we ftm0_ flt3 fxio0_d2 84 56 g8 h3 ptb3 adc0_ se13/ tsi0_ch8 adc0_ se13/ tsi0_ch8 ptb3 i2c0_sda lpuart0_ cts_b sdram_ cs0_b ftm0_ flt0 fxio0_d3 85 b11 h4 ptb4 disabled ptb4 emvsim1_ io sdram_ cs1_b ftm1_ flt0 86 c11 g1 ptb5 disabled ptb5 emvsim1_ clk ftm2_ flt0 87 f11 g2 ptb6 disabled ptb6 emvsim1_ vccen fb_ad23/ sdram_ d23 88 e11 g3 ptb7 disabled ptb7 emvsim1_ pd fb_ad22/ sdram_ d22 89 d11 g4 ptb8 disabled ptb8 emvsim1_ rst lpuart3_ rts_b fb_ad21/ sdram_ d21 90 57 e10 g5 ptb9 disabled ptb9 spi1_ pcs1 lpuart3_ cts_b fb_ad20/ sdram_ d20 91 58 d10 f1 ptb10 disabled ptb10 spi1_ pcs0 lpuart3_ rx i2c2_scl fb_ad19/ sdram_ d19 ftm0_ flt1 fxio0_d4 92 59 c10 f2 ptb11 disabled ptb11 spi1_sck lpuart3_ tx i2c2_sda fb_ad18/ sdram_ d18 ftm0_ flt2 fxio0_d5 93 60 l6 f5 vss vss vss 94 61 e7 g6 vdd vdd vdd pinout kinetis k82 sub-family, rev. 2, 11/2016 79 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode 95 62 b10 e1 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_ sout lpuart0_ rx ftm_ clkin0 fb_ad17/ sdram_ d17 ewm_in tpm_ clkin0 96 63 e9 f3 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin lpuart0_ tx ftm_ clkin1 fb_ad16/ sdram_ d16 ewm_ out_b tpm_ clkin1 97 64 d9 f4 ptb18 tsi0_ch11 tsi0_ch11 ptb18 ftm2_ch0 i2s0_tx_ bclk fb_ad15/ sdram_ a23 ftm2_qd_ pha/ tpm2_ch0 fxio0_d6 98 65 c9 e2 ptb19 tsi0_ch12 tsi0_ch12 ptb19 ftm2_ch1 i2s0_tx_ fs fb_oe_b ftm2_qd_ phb/ tpm2_ch1 fxio0_d7 99 66 f10 d1 ptb20 disabled ptb20 spi2_ pcs0 fb_ad31/ sdram_ d31 cmp0_ out fxio0_d8 100 67 f9 e3 ptb21 disabled ptb21 spi2_sck fb_ad30/ sdram_ d30 cmp1_ out fxio0_d9 101 68 f8 e4 ptb22 disabled ptb22 spi2_ sout fb_ad29/ sdram_ d29 fxio0_d10 102 69 e8 d2 ptb23 disabled ptb23 spi2_sin spi0_ pcs5 fb_ad28/ sdram_ d28 fxio0_d11 103 70 b9 c1 ptc0 adc0_ se14/ tsi0_ch13 adc0_ se14/ tsi0_ch13 ptc0 spi0_ pcs4 pdb0_ extrg usb0_ sof_out fb_ad14/ sdram_ a22 i2s0_txd1 fxio0_d12 104 71 d8 d3 ptc1/ llwu_p6 adc0_ se15/ tsi0_ch14 adc0_ se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_ pcs3 lpuart1_ rts_b ftm0_ch0 fb_ad13/ sdram_ a21 i2s0_txd0 fxio0_d13 105 72 c8 c2 ptc2 adc0_ se4b/ cmp1_in0/ tsi0_ch15 adc0_ se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_ pcs2 lpuart1_ cts_b ftm0_ch1 fb_ad12/ sdram_ a20 i2s0_tx_ fs 106 73 b8 b1 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_ pcs1 lpuart1_ rx ftm0_ch2 clkout i2s0_tx_ bclk 107 74 e5 vss vss vss 108 75 g6 vdd vdd vdd 109 76 a8 a1 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_ pcs0 lpuart1_ tx ftm0_ch3 fb_ad11/ sdram_ a19 cmp1_ out 110 77 d7 b2 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2/ lptmr1_ alt2 i2s0_rxd0 fb_ad10/ sdram_ a18 cmp0_ out ftm0_ch2 111 78 c7 c3 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_ sout pdb0_ extrg i2s0_rx_ bclk fb_ad9/ sdram_ a17 i2s0_ mclk fxio0_d14 pinout 80 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode 112 79 b7 a2 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb0_ sof_out i2s0_rx_ fs fb_ad8/ sdram_ a16 fxio0_d15 113 80 a7 b3 ptc8 cmp0_in2 cmp0_in2 ptc8 ftm3_ch4 i2s0_ mclk fb_ad7/ sdram_ a15 fxio0_d16 114 81 d6 d4 ptc9 cmp0_in3 cmp0_in3 ptc9 ftm3_ch5 i2s0_rx_ bclk fb_ad6/ sdram_ a14 ftm2_ flt0 fxio0_d17 115 82 c6 a3 ptc10 disabled ptc10 i2c1_scl ftm3_ch6 i2s0_rx_ fs fb_ad5/ sdram_ a13 fxio0_d18 116 83 c5 c4 ptc11/ llwu_p11 disabled ptc11/ llwu_p11 i2c1_sda ftm3_ch7 i2s0_rxd1 fb_rw_b fxio0_d19 117 84 b6 b4 ptc12 disabled ptc12 lpuart4_ rts_b ftm_ clkin0 fb_ad27/ sdram_ d27 ftm3_ flt0 tpm_ clkin0 118 85 a6 a4 ptc13 disabled ptc13 lpuart4_ cts_b ftm_ clkin1 fb_ad26/ sdram_ d26 tpm_ clkin1 119 86 a5 d5 ptc14 disabled ptc14 lpuart4_ rx fb_ad25/ sdram_ d25 fxio0_d20 120 87 b5 c5 ptc15 disabled ptc15 lpuart4_ tx fb_ad24/ sdram_ d24 fxio0_d21 121 88 f6 vss vss vss 122 89 e6 vdd vdd vdd 123 d5 a5 ptc16 disabled ptc16 lpuart3_ rx fb_cs5_b/ fb_tsiz1/ fb_be23_ 16_bls15_ 8_b/ sdram_ dqm2 124 90 c4 b5 ptc17 disabled ptc17 lpuart3_ tx fb_cs4_b/ fb_tsiz0/ fb_be31_ 24_bls7_ 0_b/ sdram_ dqm3 125 b4 a6 ptc18 disabled ptc18 lpuart3_ rts_b fb_tbst_ b/ fb_cs2_b/ fb_be15_ 8_bls23_ 16_b/ pinout kinetis k82 sub-family, rev. 2, 11/2016 81 nxp semiconductors 144 lqfp 100 lqfp 121 xfb ga 121 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 qspi_sip_ mode sdram_ dqm1 126 a4 b6 ptc19 disabled ptc19 lpuart3_ cts_b fb_cs3_b/ fb_be7_ 0_bls31_ 24_b/ sdram_ dqm0 fb_ta_b 127 91 d4 c6 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_ pcs0 lpuart2_ rts_b ftm3_ch0 fb_ale/ fb_cs1_b/ fb_ts_b fxio0_d22 128 92 d3 d6 ptd1 adc0_ se5b adc0_ se5b ptd1 spi0_sck lpuart2_ cts_b ftm3_ch1 fb_cs0_b fxio0_d23 129 93 c3 d7 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_ sout lpuart2_ rx ftm3_ch2 fb_ad4/ sdram_ a12 i2c0_scl 130 94 b3 a7 ptd3 disabled ptd3 spi0_sin lpuart2_ tx ftm3_ch3 fb_ad3/ sdram_ a11 i2c0_sda 131 95 a3 b7 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_ pcs1 lpuart0_ rts_b ftm0_ch4 fb_ad2/ sdram_ a10 ewm_in spi1_ pcs0 132 96 a2 c7 ptd5 adc0_ se6b adc0_ se6b ptd5 spi0_ pcs2 lpuart0_ cts_b ftm0_ch5 fb_ad1/ sdram_ a9 ewm_ out_b spi1_sck 133 97 b2 a8 ptd6/ llwu_p15 adc0_ se7b adc0_ se7b ptd6/ llwu_p15 spi0_ pcs3 lpuart0_ rx ftm0_ch6 fb_ad0 ftm0_ flt0 spi1_ sout 134 98 f6 vss vss vss 135 99 e7 vdd vdd vdd 136 100 a1 b8 ptd7 disabled ptd7 cmt_iro lpuart0_ tx ftm0_ch7 sdram_ cke ftm0_ flt1 spi1_sin 137 a10 a9 ptd8/ llwu_p24 disabled ptd8/ llwu_p24 i2c0_scl fb_a16 fxio0_d24 138 a9 c8 ptd9 disabled ptd9 i2c0_sda fb_a17 fxio0_d25 139 e4 b9 ptd10 disabled ptd10 fb_a18 fxio0_d26 140 e3 a10 ptd11/ llwu_p25 disabled ptd11/ llwu_p25 spi2_ pcs0 fb_a19 fxio0_d27 141 f4 d8 ptd12 disabled ptd12 spi2_sck ftm3_ flt0 fb_a20 fxio0_d28 142 g3 c9 ptd13 disabled ptd13 spi2_ sout fb_a21 fxio0_d29 143 g4 b10 ptd14 disabled ptd14 spi2_sin fb_a22 fxio0_d30 144 h4 a11 ptd15 disabled ptd15 spi2_ pcs1 fb_a23 fxio0_d31 pinout 82 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 5.2 recommended connection for unused analog and digital pins table 65 shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application table 65. recommended connection for unused analog interfaces pin type short recommendation detailed recommendation analog/non gpio adcx/cmpx float analog input - float analog/non gpio vref_out float analog output - float analog/non gpio dac0_out, dac1_out float analog output - float analog/non gpio rtc_wakeup_b float analog output - float analog/non gpio xtal32 float analog output - float analog/non gpio extal32 float analog input - float gpio/analog pta18/extal0 float analog input - float gpio/analog pta19/xtal0 float analog output - float gpio/analog ptx/adcx float float (default is analog input) gpio/analog ptx/cmpx float float (default is analog input) gpio/analog ptx/tsiox float float (default is analog input) gpio/digital pta0/jtag_tclk float float (default is jtag with pulldown) gpio/digital pta1/jtag_tdi float float (default is jtag with pullup) gpio/digital pta2/jtag_tdo float float (default is jtag with pullup) gpio/digital pta3/jtag_tms float float (default is jtag with pullup) gpio/digital pta4/nmi_b 10k? pullup or disable and float pull high or disable in pcr & fopt and float gpio/digital ptx float float (default is disabled) usb usb0_dp float float usb usb0_dm float float usb vout33 tie to input and ground through 10k? tie to input and ground through 10k? usb vregin tie to output and ground through 10k? tie to output and ground through 10k? usb usb0_vss always connect to vss always connect to vss vbat vbat float float vdda vdda always connect to vdd potential always connect to vdd potential vrefh vrefh always connect to vdd potential always connect to vdd potential vrefl vrefl always connect to vss potential always connect to vss potential table continues on the next page... pinout kinetis k82 sub-family, rev. 2, 11/2016 83 nxp semiconductors table 65. recommended connection for unused analog interfaces (continued) pin type short recommendation detailed recommendation vssa vssa always connect to vss potential always connect to vss potential 5.3 k82 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout 84 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vregin vout33 usb0_dm usb0_dp vss vss vddio_e pte11 pte10/llwu_p18 pte9/llwu_p17 pte8 pte7 pte6/llwu_p16 pte5 pte4/llwu_p2 vddio_e vss pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda nc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 vdd ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 vss vdd vbat extal32 xtal32 rtc_wakeup_b dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc0_se22 adc0_dm1 adc0_dp1 98 vss 97 ptd6/llwu_p15 96 ptd5 95 ptd4/llwu_p14 94 ptd3 93 ptd2/llwu_p13 92 ptd1 91 ptd0/llwu_p12 90 ptc17 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11/llwu_p11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 45. k82 100 lqfp pinout diagram pinout kinetis k82 sub-family, rev. 2, 11/2016 85 nxp semiconductors 1 a ptd7 b pte0 c pte2/ llwu_p1 d pte4/ llwu_p2 e pte6/ llwu_p16 f pte9/ llwu_p17 g pte11 h usb0_dm j vout33 k adc0_dm0 1 l adc0_dm1 2 ptd5 ptd6/ llwu_p15 pte1/ llwu_p0 pte3 pte5 pte8 pte10/ llwu_p18 usb0_dp vregin adc0_dp0 2 adc0_dp1 3 ptd4/ llwu_p14 ptd3 ptd2/ llwu_p13 ptd1 ptd11/ llwu_p25 pte7 ptd13 vss adc0_dp3 adc0_dm3 3 vref_out/ cmp1_in5/ cmp0_in5/ adc0_se22 4 ptc19 ptc18 ptc17 ptd0/ llwu_p12 ptd10 ptd12 ptd14 ptd15 nc dac0_out/ cmp1_in3/ adc0_se23 4 xtal32 5 ptc14 ptc15 ptc11/ llwu_p11 ptc16 vddio_e vdda vrefh pta20 pta21/ llwu_p21 rtc_ wakeup_b 5 extal32 6 ptc13 ptc12 ptc10 ptc9 vdd vssa vrefl nc nc vbat 6 vss 7 ptc8 ptc7 ptc6/ llwu_p10 ptc5/ llwu_p9 vdd vss vss pta11/ llwu_p23 pta2 pta5 7 pta0 8 ptc4/ llwu_p8 ptc3/ llwu_p7 ptc2 ptc1/ llwu_p6 ptb23 ptb22 ptb3 pta1 pta4/ llwu_p3 pta12 8 pta13/ llwu_p4 9 ptd9 ptc0 ptb19 ptb18 ptb17 ptb21 ptb2 pta3 pta10/ llwu_p22 pta14 9 pta15 10 ptd8/ llwu_p24 ptb16 ptb11 ptb10 ptb9 ptb20 ptb1 pta17 pta16 vss 10 vdd 11 a nc b ptb4 c ptb5 d ptb8 e ptb7 f ptb6 g ptb0/ llwu_p5 h pta29 j reset_b k pta19 11 l pta18 figure 46. k82 121 xfbga pinout diagram pinout 86 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 vdd 107 106 105 104 103 102 101 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 116 ptc11/llwu_p11 115 114 113 112 111 110 109 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 124 ptc17 123 122 121 120 119 118 117 ptc16 vdd vss ptc15 ptc14 ptc13 ptc12 132 ptd5 131 130 129 128 127 126 125 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc19 ptc18 140 ptd11/llwu_p25 139 138 137 136 135 134 133 ptd10 ptd9 ptd8/llwu_p24 ptd7 vdd vss ptd6/llwu_p15 144 143 142 141 ptd15 ptd14 ptd13 ptd12 ptb20 pta28 pta27 pta26 pta25 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb8 ptb7 pta29 ptb0/llwu_p5 ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb21 pta24 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta11/llwu_p23 pta10/llwu_p22 pta9 pta8 pta7 pta6 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pta21/llwu_p21 pta20 vss vdd vbat extal32 xtal32 rtc_wakeup_b dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc0_se22 adc0_dm1 adc0_dp1 pte17/llwu_p19 pte16 vss vddio_e pte13 pte12 pte11 pte10/llwu_p18 pte9/llwu_p17 pte8 pte7 pte6/llwu_p16 pte5 pte4/llwu_p2 vddio_e vss pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 usb0_dm usb0_dp vss pte19 pte18/llwu_p20 vssa vrefl vrefh vdda adc0_dm3 adc0_dp3 adc0_dm0 adc0_dp0 nc vregin vout33 figure 47. k82 144 lqfp pinout diagram note the 144-pin lqfp package for this product is not yet available, however it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. pinout kinetis k82 sub-family, rev. 2, 11/2016 87 nxp semiconductors 1 a ptc4/ llwu_p8 b ptc3/ llwu_p7 c ptc0 d ptb20 e ptb16 f ptb10 g ptb5 h ptb2 j reset_b k pta19 l pta18 1 2 ptc7 ptc5/ llwu_p9 ptc2 ptb23 ptb19 ptb11 ptb6 ptb1 pta29 vss vdd 2 3 ptc10 ptc8 ptc6/ llwu_p10 ptc1/ llwu_p6 ptb21 ptb17 ptb7 ptb3 ptb0/ llwu_p5 pta17 pta14 3 4 ptc13 ptc12 ptc11/ llwu_p11 ptc9 ptb22 ptb18 ptb8 ptb4 pta16 pta15 pta11/ llwu_p23 4 5 ptc16 ptc17 ptc15 ptc14 vss vss vss ptb9 pta5 pta13/ llwu_p4 pta12 pta10/ llwu_p22 5 6 ptc18 ptc19 ptd0/ llwu_p12 ptd1 vdd vdd vdd vdd pta4/ llwu_p3 pta1 pta2 pta3 6 7 ptd3 ptd4/ llwu_p14 ptd5 ptd2/ llwu_p13 vdd vddio_e vdd rtc_ wakeup_b pta0 pta21/ llwu_p21 pta20 7 8 ptd6/ llwu_p15 ptd7 ptd9 ptd12 pte5 pte10/ llwu_p18 adc0_se16 vdda vssa vbat extal32 8 9 ptd8/ llwu_p24 ptd10 ptd13 pte1/ llwu_p0 pte6/ llwu_p16 pte11 nc vrefh vrefl nc xtal32 9 10 ptd11/ llwu_p25 ptd14 pte0 pte2/ llwu_p1 pte7 vddio_e vout33 vregin adc0_dp0 adc0_dm0 dac0_out/ cmp1_in3/ adc0_se23 10 11 ptd15 pte3 pte4/ llwu_p2 pte8 pte9/ llwu_p17 vss vss usb0_dp usb0_dm adc0_dp3 adc0_dm3 vref_out/ cmp1_in5/ cmp0_in5/ adc0_se22 11 a b c d e f g h j k l vss vss vss vss figure 48. k82 121 wlcsp pinout diagram note the 121-pin wlcsp package for this product is not yet available, however it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. 6 ordering parts ordering parts 88 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: mk82. 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k82 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 1m0 = 1 mb ? 2m0 = 2 mb table continues on the next page... part identification kinetis k82 sub-family, rev. 2, 11/2016 89 nxp semiconductors field description values r silicon revision ? z = initial ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) ? lk = 80 lqfp (12 mm x 12 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 mapbga (8 mm x 8 mm) ? dc = 121 xfbga (8 mm x 8 mm x 0.5 mm) ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) cc maximum cpu frequency (mhz) ? 5 = 50 mhz ? 7 = 72 mhz ? 10 = 100 mhz ? 12 = 120 mhz ? 15 = 150 mhz ? 18 = 180 mhz n packaging type ? r = tape and reel ? (blank) = trays 7.4 example this is an example part number: mk82fn256vll15 8 terminology and guidelines 8.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. table continues on the next page... terminology and guidelines 90 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors term definition note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. 8.2 examples operating rating : operating requirement : operating behavior that includes a typical value : example example example example 8.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): terminology and guidelines kinetis k82 sub-family, rev. 2, 11/2016 91 nxp semiconductors symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v 8.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9 revision history the following table provides the revision history for this document. revision history 92 kinetis k82 sub-family, rev. 2, 11/2016 nxp semiconductors table 66. revision history rev. no. date substantial changes 0 05/2015 initial release 1 09/2015 ? updated part numbers. ? updated related resources table to include package drawing numbers and other relevant resource information. ? updated title of section 2.2.2 to 'hvd, lvd and por operating requirements'. ? updated 'v dd supply lvd and por operating requirements' table. ? added rows for v hvdh and v hvdl . ? updated 'power consumption operating behaviors' table. ? updated typ. values and max. values. ? added data for 105c. ? updated idd charts - figure 6. run mode supply current vs. core frequency and figure 7. vlpr mode supply current vs. core frequency. ? replaced section 2.2.6 'emc radiated emissions operating behaviors' with 'electromagnetic compatibility (emc) specifications'. ? removed ezport information from 'general switching specifications' table. ? updated 100 lqfp and 121 xfbga values in the 'thermal attributes' table. ? updated 'mcg specifications' table ? updated typ. value of fdco_t from -1 to 1. ? removed j acc_fll data. ? updated description of i pll and their corresponding typ. values. ? updated typ. values of j cyc_pll and j acc_pll . ? updated footnote 2 in 'sdram timing (full voltage range)' table - corrected maximum frequency of fb_clk to 75mhz. ? removed i alkg data from 'comparator and 6-bit dac electrical specifications' table. ? updated min and max values of s freq in the 'timing specifications, high drive strength' table. ? updated the 'timing requirements for power-down sequence' table. ? added a footnote - "frtcclk is erclk32k, and this clock must be enabled during the power down sequence." ? updated unit from ns to s. ? added 121 wlcsp pin assignment information and diagram to the pinout section. 2 11/2016 ? added 'device revision number' table. ? removed phrase "(except rtc_wakeup pins)" from r pu and r pd rows in 'voltage and current operating behaviors' table. ? updated 'power consumption operating behaviors' table ? updated typ. and max. values of i dd_run run mode current all peripheral clocks enabled. ? updated footnote 3 to "120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled". ? in 'thermal operating requirements' table, in footnote corrected t j = t a + ja to t j = t a + r ja . revision history kinetis k82 sub-family, rev. 2, 11/2016 93 nxp semiconductors how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer ? s technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2015 - 2016 nxp b.v. document number k82p121m150sf5 revision 2, 11/2016 |
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